I. Field of the Disclosure
The technology of the disclosure relates generally to dynamic logic circuits clocked by a clock signal, and more particularly to increasing speed performance of dynamic logic circuits.
II. Background
Dynamic logic circuits provide significant performance advantages in comparison to static logic circuits. Dynamic logic circuits reduce transistor gate capacitance during a logic evaluation. In this regard, as an example, a conventional processor contains many instances of dynamic logic circuits throughout its design in performance-critical logic to provide faster evaluation of logic evaluations.
In this regard, FIG. 1 is a circuit diagram of a NAND dynamic logic circuit 100 as an example of a dynamic logic circuit. The NAND dynamic logic circuit 100 pre-charges a dynamic node (DYN) 102 voltage in a pre-charge phase. The dynamic node (DYN) 102 is pre-charged to voltage Vdd with a P-type Field-Effect Transistor (PFET) 104 in a pre-charge circuit 106 when a clock signal (CLK) 108 is low to provide the voltage Vdd at the dynamic node (DYN) 102. This is because the PFET 104 passes a strong logical “1” or voltage Vdd so that the dynamic node (DYN) 102 is charged to voltage Vdd, as opposed to only a threshold voltage Vt below voltage Vdd if employing an N-type FET (NFET) for example. The voltage Vdd at the dynamic node (DYN) 102 transitions an output node (OUT) 110 to ground voltage (GND) because of an inverter 112.
Then, once the clock signal 108 transitions high in an evaluation phase, the PFET 104 in the pre-charge circuit 106 becomes inactive. The NAND dynamic logic circuit 100 evaluates the logic with N-type FETs (NFETs) 114(1), 114(2) in a pull-down logic circuit 116, based on inputs A and B, respectively, so that the evaluation phase will evaluate quickly. If the states of inputs A and B are input A=voltage Vdd and input B=voltage Vdd, the NFETs 114(1), 114(2) in the pull-down logic circuit 116 will be active. This causes the series-connected NFETs 114(1), 114(2), 118 in the evaluation phase to pull the dynamic node (DYN) 102 to ground voltage (GND), resulting in the output node (OUT) 110 transitioning to voltage Vdd. Otherwise, if input A=ground voltage GND or input B=ground voltage GND, the dynamic node (DYN) 102 voltage remains at voltage Vdd during the evaluation phase due to a stacked PFET keeper circuit 120 retaining the dynamic node (DYN) 102 at voltage Vdd. Consequently, the output node (OUT) 110 remains at ground voltage (GND) because of the inverter 112, respectively.